1. Field of the Invention
This invention pertains to a digital switching system and more particularly to an apparatus for setting the stage number of ATM (Asynchronous Transfer Mode) channels, according to a multi-stage self-routing method, to integrally switch information having different traffic characteristics, such as moving images, numerical data and voices, by using an ATM transmission system like a broadband ISDN.
2. Description of the Related Art
With the widespread use of data communication, public switched networks are now required to execute high-quality data communication, as well as the traditional voice communication.
A Broadband Integrated Services Digital Network (B-ISDN) has begun to be utilized as a communication network, not only for low-speed data, such as voice data, but also for high-speed data between 150 Mbps and 600 Mbps, such as moving images, and various interfaces have begun to be standardized. CCITT (International Telegraph and Telephone Consultative Committee) is currently working on its advisory report on an ATM transmission system, which is an essential technology for realizing a B-ISDN, to be submitted in 1992.
An ATM communication network transmits and exchanges information of different bands divided and housed in fixed-length data units called cells, to which headers are added. A header contains a virtual channel identifier (VCI) for identifying the receiving side subscriber. Thus, an ATM switching system uses the headers to enable hardware to transfer and switch cells to the receiving side subscriber at high speed. This makes it possible to flexibly provide services requiring different transmission speeds, and to efficiently utilize transmission paths.
In this switching operation, a switching system processor designates the buffer the switches of the ATM switching system to which cells are to be written according to the VCI attached to a cell, utilizing. The cells flow autonomously in the network according to this designation. Hence, this switching operation is called a self-routing (SR). The receiving side subscriber extracts necessary cells flowing over ATM highways based on the VCIs attached to cells, and restores user information by eliminating headers from the cells.
FIG. 1 is a schematic view of a generic ATM switching system.
In FIG. 1, a plurality of trunks 2 accommodate respective subscriber lines 1 on the input side. A plurality of multiplexers (MUXs) 3 partially multiplex respective outputs from the input trunks 2. #1 through #4 of input highways 4 receive outputs from the corresponding multiplexers 3. A virtual channel controller (VCC) 5 accommodates the input highways 4. Based on the call control information inputted from a central processor (CC) 13 of the switching system through a controller interface (CPIF) 12, the VCC 5 exchanges the VCIs (information specifying the destination) attached to the headers of the received cells from the respective input highways 4, with new VCIs specifying the next output node (ATM exchanger). At the same time, the VCC 5 adds to the head ends of the cells information specifying the path over which the cells are to be switched to be outputted to destined output highways 8 in a data format called tags. This will be described later.
A multi-stage self-routing channel (MSSR) 6, a virtual channel, receives respective outputs from the VCC 5. The MSSR 6 comprises a plurality of self-routing modules (SRMs) 7. In the example shown in FIG. 1, the MSSR 6 has a 2.times.3 configuration in which two (2) rows and three (3) stages of SRMs 7 are provided. The SRMs 7 in the first stage are #1.sub.1 and #1.sub.2, those in the second stage are #2.sub.1 and #2.sub.2, and those in the third stage are #3.sub.1 and #3.sub.2. The configuration of the SRMs 7 are further elaborated later.
The MSSR 6 outputs cells to #1 through #4 of the output highways 8, which are connected to respective demultiplexers (DMUXs) 9, which demultiplex the cells and output the demultiplexed cells to subscriber lines 11 on the output side through output trunks 10 corresponding to the respective DMUXs 9.
FIG. 1 shows a configuration where cells flow in a single direction over the channels. It goes without saying that channels for cells flowing in the opposite directions can be configured similarly.
FIG. 2 shows an exemplary configuration of one of the SRMs 7 shown in FIG. 1.
In the example shown in FIG. 2, an SRM 7 has two (2) input lines and two (2) output lines, and switches SW1.sub.1, SW1.sub.2, SW2.sub.1 and SW2.sub.2 are provided at the four (4) crossing points of the input lines and output lines. That is, the four (4) switches of an SRM 7 correspond with two (2) input lines and two (2) output lines. Although an actual channel comprises more input lines and more output lines in reality, since their basic connections are entirely similar to those in the example shown in FIG. 2, the SRMs 7 are explained by referring to the 2.times.2 exemplary configuration having two (2) input lines and two (2) output lines.
FIG. 3 shows the configuration of one of the above switches SW1.sub.1 through SW2.sub.2.
In FIG. 3, by identifying the (later described) tags of supplied ATM cells, a header checker 14 judges whether or not the switch should accept the ATM cells. When the header checker 14 decides to accept the ATM cells, a cell buffer 15 of the switch stores the ATM cells. A multiplexer 16 of the switch multiplexes the ATM cells thus stored at a cell timing for output over an highway on the output side, thereby completing the switching operation. When the header checker 14 does not decide to accept the ATM cells, they are sent to the next switch over a line branching before the header checker 14.
Next, FIGS. 4A and 4B show the data configuration of the ATM cells handled by the ATM switching system shown in FIG. 1.
An ATM cell normally has the following data. As shown in FIG. 4A, an ATM cell has an information part 18, with e.g. forty-eight (48) octets, for storing communication information. An ATM cell also has a header part 17, with e.g. five (5) octets, for storing a VCI or a VPI (the address information for the receiving side subscriber), a CRC code for error correction, information specifying the payload type of the cell, and information indicating whether or not the cell should be abandoned during a congestion. An ATM cell also has a tag part 19, with e.g. one (1) octet for storing information of the path in the MSSR 6 over which the ATM cell should be routed to, be outputted to the destined one of the output highways 8. The VCC 5 shown in FIG. 1 attaches the tag part 19 to the ATM cells it receives.
FIG. 4B shows the configuration of the tag part 19 shown in FIG. 4A.
A tag information part 19 has three (3) stages of two (2) bit tag data 20 for having the respective switches SW1.sub.1 through SW2.sub.2 (see FIG. 2.) in each of the three (3) stage SRMs 7 #1.sub.1 through #3.sub.2 select ATM cells.
FIG. 5 shows a relation between tag data and a transmission path.
FIG. 6 shows an exemplary configuration of tag data.
The examples shown in FIGS. 5 and 6 are referred to in explaining how the MSSR 6 selects a path for transmitting ATM cells according to tag data 20.
FIG. 1 shows an example where #1.sub.1 through #3.sub.2 of the SRMs 7 in the MSSR 6 are pair-connected in three (3) stages. FIG. 2 shows an example, where respective SRMs 7 have the four (4) switches SW1.sub.1 through SW2.sub.2. FIG. 5 shows the relations among all of the six (6) SRMs 7 #1.sub.1 through #3.sub.2.
Here, the header checker 14 (see to FIG. 3.) in each of the four (4) switches SW1.sub.1 through SW2.sub.2 respectively in #1.sub.1 and #1.sub.2 of the SRMs 7 in the first stage refers to the first stage two (2) bit tag data 20 (Refer to FIG. 4B.) in the tag part 19 attached to the supplied ATM cells. If the value of the tag data 20 is 1 ("01" in binary expression), switches SW1.sub.1 and SW1.sub.2 in #1.sub.1 and #1.sub.2 of the first stage SRMs 7 have respective cell buffers 15 (Refer to FIG. 3.) receive ATM cells. If the value of the tag data 20 is 2 ("10" in binary expression), switches SW2.sub.1 and SW2.sub.2 in #1.sub.1 and #1.sub.2 of the first stage SRMs 7 have respective cell buffers 15 (Refer to FIG. 3.) receive ATM cells.
The header checker 14 in each of the four (4) switches SW1.sub.1 through SW2.sub.2 in the respective ones of the second stage SRMs 7 #2.sub.1 and #2.sub.2 refers to the second stage two (2) bit tag data 20 in the tag part 19 attached to the supplied ATM cells. Similarly to the above case of the first stage, either pair of switches SW1.sub.1 and SW1.sub.2 or SW2.sub.1 and switches SW2.sub.2 in #2.sub.1 and #2.sub.2 of the second stage SRMs 7 buffer the ATM cells.
The header checker 14 in each of the four (4) switches SW1.sub.1 through SW2.sub.2 in the respective ones of the third stage SRMs 7 #3.sub.1 and #3.sub.2 refers to the second stage two (2) bit tag data 20 in the tag part 19 attached to the supplied ATM cells. Similarly to the above cases of the first and second stages, either pair of switches SW1.sub.1 and SW1.sub.2 or switches SW2.sub.1 and SW2.sub.2 in #3.sub.1 and #3.sub.2 of the third stage SRMs 7 buffer the ATM cells.
The above explanation describes a case in which the respective SRMs 7 comprise four (4) switches SW1.sub.1 through SW2.sub.2. Here, for example, #1 of the input highways 4 can select either switch SW1.sub.1 or switch SW2.sub.1 in #1.sub.1 of SRMs 7. However, in an actual switching system, respective SRMs 7 comprise sixteen (16) switches in response to four (4) input lines and four (4) output lines, and an input highway can select one of four (4) switches SW1.sub.1 through SW2.sub.2. As shown in FIG. 4B, it is possible to select one from them using two (2) bit tag data 20 in respective stages.
Assume now that the tag data 20 attached to tag part 19 of an ATM cell inputted from #1 of the input highways 4 shown in FIG. 5 is as shown in FIG. 6. In this case, the ATM cells are transmitted over the path shown as a kinked bold line shown in FIG. 5.
That is, an ATM cell inputted from #1 of the input highways 4 is supplied to switches SW1.sub.1 and SW2.sub.1 in #1.sub.1 of the SRMs 7, as shown in FIG. 5. Here, assume also that a register (not shown in FIG. 5) in the header checker 14 in the respective switches is provided with information that the switches SW1.sub.1 and SW2.sub.1 are set in #1.sub.1 of the first stage SRMs 7. Thus, the respective header checkers 14 in switches SW1.sub.1 and SW2.sub.1 in #1.sub.1 of SRMs 7 recognize the value "01" (Refer to FIG. 6.) of the two (2) bit tag data 20 in the first stage of the tag part 19 of the supplied ATM cell. This causes the cell buffer 15 (FIG. 3) of only SW1.sub.1 to receive the supplied ATM cell. The corresponding one of the multiplexers (MUXs) 16 (FIG. 3) multiplexes the ATM cell stored in the cell buffer 15 at a predetermined cell timing over the output highway towards switch SW1.sub.2.
The ATM cell thus multiplexed is supplied to switches SW1.sub.1 and SW2.sub.1 in #2.sub.1 of the second stage SRMs 7 through the multiplexer 16 (FIG. 3) in switch SW1.sub.2 in #1.sub.1 of the SRMs 7. Here, it is assumed that a register (not shown in FIG. 5) in the header checker 14 in the respective switches is provided with information that the switches SW1.sub.1 and SW2.sub.1 are set in #2.sub.1 of the second stage SRMs 7. Thus, the respective header checkers 14 in switches SW1.sub.1 and SW2.sub.1 in #2.sub.1 of the second stage SRMs 7 recognize the value "10" (Refer to FIG. 6.) of the two (2) bit tag data 20 of the tag part 19 of the supplied ATM cell. This causes the cell buffer 15 (FIG. 3) of only SW2.sub.1 to receive the supplied ATM cell. The corresponding one of the multiplexers (MUXs) 16 (FIG. 3) multiplexes the ATM cell stored in the cell buffer 15 at a predetermined cell timing over the output highway towards switch SW2.sub.2.
The ATM cell thus multiplexed is supplied to switches SW1.sub.1 and SW2.sub.2 in #3.sub.2 of the third stage SRMs 7 through the multiplexer 16 (FIG. 3) in switch SW2.sub.2 in #2.sub.1 of the SRMs 7. Here, it is assumed that a register (not shown in FIG. 5) in the header checker 14 in the respective switches is provided with information that the switches SW1.sub.1 and SW2.sub.2 are set in #3.sub.2 of the third stage SRMs 7. Thus, the respective header checkers 14 in switches SW1.sub.1 and SW2.sub.2 in #3.sub.2 of the third stage SRMs 7 recognize the value "10" (Refer to FIG. 6.) of the two (2) bit tag data 20 of the tag part 19 of the supplied ATM cell. This causes the cell buffer 15 (FIG. 3) of only SW2.sub.1 to receive the supplied ATM cell. The corresponding one of the multiplexers (MUXs) 16 (FIG. 3) multiplexes the ATM cell stored in the cell buffer 15 at a predetermined cell timing over #4 of the output highways 8 to be outputted from the switching system.
As described above, switches SW1.sub.1 through SW2.sub.2 in the respective stage SRMs 7 of the MSSR 6 recognize the tag part 19 at different bit positions (Refer to FIG. 4B.) in the tag data 20. Therefore, each of the SRMs 7 needs to have a stage number indicating its module stage.
FIG. 7 shows a first prior art configuration for setting stage numbers to the respective SRMs 7 shown in FIG. 1.
In the first prior art configuration, the stage numbers of the SRMs 7 is determined in a hardware manner e.g. by two kinds of stage number setting signals ST0 and ST1 supplied from a stage number setter 21 in each of the SRMs 7 as fixed voltages. That is, when the stage number is set to 1, for example, the stage number setter 21 outputs a high level voltage and a low level voltage, respectively, as stage number setting signals ST0 and ST1. The stage number setter 21 generates stage number setting signal ST0 having a positive voltage supplied through a resistor R from a power source V.sub.CC and stage number setting signal ST1 having the earth voltage. Stage number setting signals ST0 and ST1 thus obtained set stage numbers to registers (not shown) in the header checkers 14 respectively in four (4) switches SW1.sub.1 through SW2.sub.2 (FIG. 2) in the SRM 7 to which the stage number setter 21 belongs. Thence, the earlier described switching operations are performed.
FIG. 8 shows a second prior art configuration for setting stage numbers in the respective SRMs 7 shown in FIG. 1.
In the second prior art configuration, two kinds of stage number setting signals ST0 and ST1 supplied from a stage number setter 22 in each of the SRMs 7 determine the stage numbers of the SRMs 7. In this case, two dip switches S in the stage setter 22 change stage number setting signals ST0 and ST1 for respective SRMs 7. That is, when the stage number is set to 1, for example, the stage number setter 22 has dip switches S to be turned off for stage number setting signal ST0 and on for stage number setting signal ST1. The stage number setter 22 generates stage number setting signal ST0 having a positive voltage supplied through a resistor R from a power source V.sub.CC and stage number setting signal ST1 having the earth voltage. Stage number setting signals ST0 and ST1 thus obtained set stage numbers to registers (not shown) in the header checkers 14 respectively in four (4) switches SW1.sub.1 through SW2.sub.2 (FIG. 2) in the SRM 7 to which the stage number setter 22 belongs. Thence, the earlier described switching operations are performed, as with the first prior art configuration.
However, the first prior art configuration shown in FIG. 7 causes the stage number setters 21 in respective stages to be configured differently, although basically the six (6) SRMs 7 in the three (3) stages have scant functional differences. Since a hardware combination for a particular stage cannot be used for another, the first prior art configuration has a problem that parts for the SRMs cannot be commonly designed, thereby preventing SRM 7 in a stage from being applied to another stage and thus lacking in flexibility.
On the other hand, the second prior art configuration shown in FIG. 8 has dip switches S in stage number setter 22 freely change stage numbers of the respective SRMs 7, thereby enabling SRM 7 in a stage to be used in another stage. However, when a stage number is set incorrectly, respective switches in the SRM 7 recognize incorrect bit positions of the tag data 20. (Refer to FIG. 4B.) Therefore, the second prior art configuration has the problem that the MSSR 6 as a whole might cause a severe fault, such as discarding ATM cells and outputting ATM cells to wrong output highways. The higher the number of the SRMs in an MSSR, the more likely such an occurrence is.